The present invention relates to a semiconductor device including a trench gate type insulated gate bipolar transistor (to be simply referred to as an IGBT hereinafter).
In recent years, a low loss in power semiconductor elements is commercially required more and more. To obtain a lower ON voltage, trench gate IGBTs are put into practical use.
The trench gate IGBT can attain a low ON voltage characteristic because the channel resistance is low due to smaller cell size than in a traditional planar gate IGBT, the structure does not have any parasitic JFET (Junction Field Effect Transistor), unlike the planar gate IGBT, and no voltage drop by the pinch-off effect occurs.
FIG. 10 shows the basic sectional structure of a conventional trench gate IGBT.
A lightly doped, high-resistance n-type semiconductor layer 12 is formed on a p+-type semiconductor substrate 11. A p-type base layer 13 about 4 μm deep is formed in the surface portion of the n−-type semiconductor layer 12. An n+-type emitter layer 14 about 0.5 μm deep is formed in the surface portion of the p-type base layer 13 by impurity diffusion.
Trenches about 1 μm wide and about 6 to 7 μm deep are selectively formed by RIE (Reactive Ion Etching). A polysilicon layer or the like about 0.5 μm thick is formed on a gate insulating film 15 about 0.1 μm thick, and buried in each trench. The surface of the buried layer is planarized to form a gate electrode 16.
An emitter electrode 17 which ohmic-contacts both the p-type base layer 13 and n+-type emitter layer 14 is formed. A collector electrode 18 is formed on the lower surface of the p+-type semiconductor substrate 11.
A reference which discloses a technique for a conventional IGBT is as follows:
Japanese Patent Laid-Open No. 2001-168333
The conventional trench gate IGBT suffers the following problems.
The area of the p-type base layer 13 is large, and the discharge effect of holes injected from the p+-type semiconductor substrate 11 to the n−-type semiconductor layer 12 is high. An effect of injecting electrons from the emitter layer 14 so as to compensate for holes in accordance with the charge neutralization condition is weak. The conductivity modulation of the high-resistance n−-type semiconductor layer 12 is not satisfactory, failing to reduce the ON voltage.
Also in turn-off which is an event of discharging carriers, the loss cannot be fully reduced.